Implementing electronic circuits involves connecting isolated devices through specific electronic paths. To fabricate an integrated circuit (IC), manufacturers isolate devices from one another within the semiconductor matrix. Subsequent interconnection of the isolated devices creates the desired circuit configurations and functionality. To reduce IC product cost, manufacturers need to pack the devices in ever closer proximity within a silicon wafer to increase the number of devices produced per silicon wafer processed. Unfortunately, the increased packing density creates larger parasitic inter-device currents resulting in degraded device performance. Device isolation technology addresses these performance issues and has thus become a critical aspect of contemporary integrated circuit fabrication.
Over the last few decades, manufacturers have developed a variety of successful isolation technologies to address the requirements of different integrated circuit types such as NMOS, CMOS, bipolar and BiCMOS. In general, the various isolation technologies exhibit different attributes with respect to such characteristics as defect density generated during isolation processing, minimum isolation spacing, surface planarity, process complexity and device performance. Moreover, manufacturers commonly trade off some of these characteristics when developing an isolation process for a particular integrated circuit application to optimize device performance, process cycle times and product cost.
In metal-oxide-semiconductor (MOS) technology, manufacturers design isolation structures to prevent parasitic channel formation between adjacent devices, such devices being primarily NMOS or PMOS transistors or CMOS circuits. LOCOS (an acronym for LOCal Oxidation of Silicon) isolation has become the most widely used isolation technology for MOS circuits. LOCOS isolation essentially involves the growth of silicon dioxide (SiO.sub.2 or oxide) in field regions of the silicon substrate to produce the so-called field oxide (FOX). In LOCOS isolation, masked areas of the substrate generally define active regions, which contain the devices, and unmasked areas, which contain the inactive FOX in recessed or semirecessed structures. Manufacturers typically grow FOX to a thickness sufficient to reduce parasitic capacitance over the FOX regions while, at the same time, maintaining a desired level of surface planarity. The great success of LOCOS isolation technology is to a large extent attributed to its inherent simplicity in MOS process integration, cost effectiveness and adaptability.
In spite of its success, there are several important limitations of LOCOS technology that motivate development of improved or alternative isolation structures. Active area features defined by FOX growth often deviate from the intended structures because of nonideal LOCOS processing effects. For example, light diffraction and interference from mask edges during the photolithographic patterning process produce rounding at mask corners, an effect exacerbated by the small features found in DRAM active area arrays. Additionally, proper mask alignment is often difficult to achieve because of the nonplanar surfaces that result from LOCOS isolation structures. Mask misalignment can cause lifting and nonuniformities in isolated, narrow structures defined by the masking process. Moreover, LOCOS isolation creates oxide undergrowth, or encroachment, at the edge of the masking stack that defines the active regions of the substrate. This so-called bird's beak (as it appears in cross section) occupies a portion of the active region without providing useful device isolation and thus degrades device performance. The bird's beak similarly limits device density because it takes up active region space without providing any functionality. Moreover, bird's beak growth becomes increasingly problematic for active region features in the sub half-micron regime.
In conventional LOCOS, isolation structures are made principally from silicon dioxide by oxidizing portions of the silicon substrate. Heating the substrate for a period of time in an oxidizing ambient produces high quality thermal oxides. Unfortunately, growing silicon dioxide from a single crystal silicon substrate creates a volume expansion of the silicon dioxide layer. This volume expansion creates stress on the adjacent substrate resulting in stress-induced defects which contribute to parasitic leakage currents. The volume expansion similarly causes field oxide regions to extend above the substrate surface, compromising surface planarity for subsequent device processing. From a manufacturing viewpoint, growing high-quality, uniform silicon dioxide field isolation is a time-consuming, expensive process.
In the continuing trend toward higher density and higher performance integrated circuits, effective field isolation on submicron and nanometer scales remains one of the most difficult challenges facing semiconductor manufacturers. While conventional LOCOS processes have sufficed in the past, there remains a critical need for improved, cost-effective field isolation processes.